Spin-transfer torque (STT) random access memory (RAM) is a potential alternative to on-chip SRAM for mobile applications, and as a replacement for DRAM and NOR-flash. It offers the attributes of fast read-write, high endurance, and non-volatility with good endurance and low power consumption.
One of the major challenges facing STT-RAM involves the patterning of the magnetic stack in a dense array. Electrically conductive non-volatile by-products condense on the sidewall of the structure and electrically shunt the magnetic tunnel junction. In addition, as the dimension of the device is scaled to below 40 nm in width, etch-induced damage edge of the magnetic tunnel junction degrades the performance of the device. Finally, for dense structures, near vertical sidewalls are desired to ensure electrical isolation between adjacent bits. Thus, there is an urgent need to develop a non-damaging etch process to pattern the STT-RAM stack, especially as the dimensions are scaled down from 40 nm to sub 20 nm.